The present invention relates to a solid-state image pickup device and, more particularly, to a solid-state image pickup device comprising pixels arranged in two dimensions.
A two-dimensional solid-state image pickup device, where the pixels are arranged to form a matrix (with rows and columns), and in which each pixel includes a photoelectric converting element, such as a photodiode, and means for drawing out photoelectric charges generated in the photoelectric converting element onto an output signal line, have had a wide variety of applications. Such solid-state image pickup devices can be subdivided into a CCD type and a MOS type depending on the means for reading put (drawing out) the photoelectric charges generated in the photoelectric converting element. In a CCD image pickup device, the photoelectric charges are transferred while being accumulated in potential wells. In a MOS image pickup device, on the other hand, charges accumulated in the pn junctions capacitance of a photodiode are read out by means of a MOS transistor.
The structure of each pixel in a conventional MOS solid-state image pickup device will be described next in reference to FIG. 13. In the drawing, PD denotes a photodiode and Tr1 denotes an n-channel MOS transistor having a drain connected to the cathode of the photodiode PD, a source connected to an output signal line Lsig, and a gate connected to a column select line Lvsel. When light is incident upon the photodiode PD, charges proportional to the quantity of incident light are generated and accumulated (integrated) in the pn junction capacitance of the photodiode PD. At the completion of the integration process, a high voltage is applied to the column select line Lvsel to bring the transistor Tr1 into the ON state. Upon the turning ON of the transistor Tr1, the charges accumulated in the pn junction capacitance of the photodiode PD are outputted to the output signal line Lsig to be read, out.
However, the aforesaid CCD solid-state image pickup device has the drawback of a narrow dynamic range because only the potential of the charges generated in the photodiode is accumulated and transferred. On the other hand, the conventional MOS solid-state image pickup device has several drawbacks including: an insufficiently wide dynamic rangexe2x80x94albeit wider than the dynamic range of the CCD solid-state image pickup devicexe2x80x94because the charges generated in proportion to the quantity of incident light are accumulated in the pn junction capacitance of the photodiode; a degraded S/N ratio (signal-to-noise characteristic), due to switching noise which results from the reading operation performed by switching the MOS transistor; and, differences in the time of integration between pixels because the reading operation is performed by switching the MOS transistor for each of the pixels sequentially. Specifically, when the respective MOS transistors for two photodiodes are sequentially activated, as shown in FIG. 12, the turning ON of a second MOS transistor (e.g., Tr5), which corresponds to a column select line that is subsequent to the column select line Lvsel connected to the transistor Tr1, the turning on of transistor Tr5 lags behind the turning ON of the transistor Tr1. Although integration in a photodiode connected to the transistor Tr5 is initiated simultaneously with integration in the photodiode PD connected to the transistor Tr1, provided that light is incident concurrently, the reading operation from the transistor Tr1 leads the reading operation from the transistor Tr5 due to the switching time difference, so that an integration time in the transistor Tr1 is different from an integration time in the transistor Tr5.
It is therefore an object of the present invention to provide a two-dimensional solid-state image pickup device with a sufficiently wide dynamic range. Another object of the present invention is to provide a two-dimensional solid-state image pickup device wherein all pixels can be integrated with the same timing.
These and other objects of the present invention are achieved by a two-dimensional solid-state image pickup device comprising pixels arranged to form a matrix, each of the pixels including: a photodiode; a first MOS transistor having a first electrode and a gate electrode each connected to one electrode of the photodiode, the first MOS transistor operating in a subthreshold region; a second MOS transistor having a gate electrode connected to the gate electrode of the first MOS transistor, the second MOS transistor operating in the subthreshold region; a capacitor having one terminal connected to a second electrode of the second MOS transistor and the other terminal connected to a fixed voltage, the capacitor being reset via the second MOS transistor when a reset voltage is supplied to a first electrode of the second MOS transistor; and a third MOS transistor for read operation having a first electrode connected to the one terminal of the capacitor, a second electrode connected to an output signal line, and a gate electrode connected to a column select line.
In this arrangement, a photoelectric current generated in the photodiode is logarithmically converted in the first MOS transistor and the gate voltage thereof becomes proportional to the current through logarithmic conversion. The voltage is used to charge the capacitor through the second MOS transistor. At the completion of integration, the third MOS transistor is turned ON and a voltage on the capacitor is led out onto the output signal line. Afterward, when the reset voltage is applied to the first electrode of the second MOS transistor, the voltage on the capacitor is reset to a reset value and integration in the capacitor is initiated again.
The objects of the present invention may also be achieved by a two-dimensional solid-state image pickup device comprising pixels arranged to form a matrix, each of the pixels including: a photodiode; a first MOS transistor having a first electrode and a gate electrode each connected to one electrode of the photodiode, the first MOS transistor operating in a subthreshold region; a second MOS transistor having a gate electrode connected to the gate electrode of the first MOS transistor and a first electrode connected to a direct-current voltage, the second MOS transistor operating in the subthreshold region; a capacitor having one terminal connected to a second electrode of the second MOS transistor and the other terminal connected to a fixed voltage, the capacitor integrating a signal based on photoelectric charges generated in the photodiode; a third MOS transistor for read operation having a first electrode connected to the one terminal of the capacitor, a second electrode connected to an output signal line, and a gate electrode connected to a column select line; and a fourth MOS transistor having a first electrode connected to the one terminal of the capacitor and a second electrode connected to a direct-current voltage, the fourth MOS transistor being turned ON in response to a reset pulse applied to a gate electrode thereof to reset the capacitor to an initial state.
In this arrangement, the integration in the capacitor and the reading of a voltage from the capacitor are performed in the same manner as in the case of the first embodiment; however, the resetting of the capacitor is performed by turning ON the fourth MOS transistor that is connected in parallel with the capacitor. Accordingly, the resetting of the capacitor is performed more accurately at a higher speed.
The objects of the present invention may also be achieved by a two-dimensional solid-state image pickup device comprising pixels arranged to form a matrix, each of the pixels including: a photodiode; a first MOS transistor having a first electrode and a gate electrode each connected to one electrode of the photodiode, the first MOS transistor operating in a subthreshold region; a second MOS transistor having a gate electrode connected to the gate electrode of the first MOS transistor and a first electrode connected to a direct-current voltage, the second MOS transistor operating in the subthreshold region; a capacitor having one terminal connected to receive a signal from a second electrode of the second MOS transistor and the other terminal connected to a fixed voltage, the capacitor integrating a signal based on photoelectric charges generated in the photodiode; a third MOS transistor for read operation having a first electrode connected to the one terminal of the capacitor, a second electrode connected to an output signal line, and a gate electrode connected to a column select line; and a fourth MOS transistor having a first electrode connected to the one terminal of the capacitor and a second electrode connected to a direct-current voltage, the fourth MOS transistor being constantly in the ON state with a direct-current voltage applied to a gate thereof.
In this arrangement, the fourth MOS transistor, which is constantly in the ON state, is essentially equivalent to a resistor having a specified value so connected to the capacitor. Consequently, an initial value in the capacitor is determined by the resistor. In other words, the initial value in the capacitor can be adjusted by varying a direct-current voltage applied to the gate electrode of the fourth MOS transistor.
The objects of the present invention may also be achieved by a two-dimensional solid-state image pickup device comprising pixels arranged to form a matrix, each of the pixels including: a photoelectric converting element; logarithmic converting means for changing an output current from the photoelectric converting element into a logarithmically converted voltage; a MOS transistor having a gate electrode to which the output voltage from the logarithmic converting means is applied; a capacitor having one terminal connected to receive an output current from a second electrode of the MOS transistor via first switching means and the other terminal connected to a fixed voltage; and second switching means connected to the one terminal of the capacitor and to an output signal line, wherein integration in the capacitor is performed by turning ON the first switching means and turning OFF the second switching means, a voltage is led out from the capacitor onto the output signal line by turning OFF the first switching means and turning ON the second switching means, and the capacitor is reset with the application of a reset voltage to a first electrode of the MOS transistor by turning ON the first switching means and turning OFF the second switching means.
This arrangement allows the reading operations to be performed with respect to each of the pixels by simultaneously turning OFF the first switching means for each of the pixels, and then turning ON the second switching means for each pixel to be read. Thus, the integration time can be equalized for each of the pixels. In other words, the integration time can be equalized for each of the pixels since it is possible to initiate integration by simultaneously turning ON the first switch and then complete the integration by simultaneously turning OFF the first switch.
The objects of the present invention may also be achieved by a two-dimensional solid-state image pickup device comprising pixels arranged to form a matrix, each of the pixels including: a photoelectric converting element; logarithmic converting means for changing an output current from the photoelectric converting element into a logarithmically converted voltage; a MOS transistor having a gate electrode to which the output voltage from the logarithmic converting means is applied; a capacitor having one terminal connected to receive an output current from a second electrode of the MOS transistor via first switching means and the other terminal connected to a fixed voltage; second switching means for read operation connected to the one terminal of the capacitor and to an output signal line; and resetting means connected to the one terminal of the capacitor, wherein charges are accumulated in a pn junction capacitance of the MOS transistor while a voltage on the capacitor is read therefrom by turning OFF the first switching means and the first switching means is turned ON after the completion of the read operation to transfer the charges from the pn junction capacitance to the capacitor.
This arrangement not only equalizes the timing for integration for each of the pixels like the forth embodiment, but also allows signal integration to be performed by using the pn junction capacitance of the MOS transistor during the time of the reading operation. After the reading operation is completed, the charges accumulated in the pn junction capacitance can be transferred to the capacitor so that the charges are continuously accumulated in the capacitor (integration). By thus performing a part of the integration process in parallel with the read operation, a solid-state image pickup device with excellent responsivity is implemented to provide a reduced exposure time.
The objects of the present invention may also be achieved by a two-dimensional solid-state image pickup device comprising pixels arranged to form a matrix, each of the pixels including: a photoelectric converting element; logarithmic converting means for changing an output current from the photoelectric converting element into a logarithmically converted voltage; a MOS transistor having a gate to which the output voltage from the logarithmic converting means is applied; a capacitor having one terminal connected to receive an output current from a second electrode of the MOS transistor via first switching means and the other terminal connected to a fixed voltage; second switching means for read operation connected to the one terminal of the capacitor and to an output signal line; and resetting means connected to the one terminal of the capacitor, wherein integration in the capacitor is performed by turning ON the first switching means and turning OFF the second switching means, while a voltage on the capacitor is read therefrom onto the output signal line by turning OFF the first switching means and turning ON the second switching means, a pn junction capacitance of the MOS transistor in which charges based on a photoelectric current are accumulated is reset with the application of a reset voltage to a first electrode of the MOS transistor and then integration in the pn junction capacitance is initiated, the capacitor is reset by the resetting means after turning OFF the second switching means, charges are transferred from the pn junction capacitance to the capacitor by turning ON the first switching means, and integration in the capacitor is subsequently performed based on the photoelectric current.
The arrangement above is essentially the same as the one previously described to the extent that the timing for integration can be equalized for each of the pixels and responsivity can be improved. In addition, the present arrangement performs the resetting of the pn junction capacitance of the MOS transistor and the resetting of the capacitor by using the separate and distinct means. Specifically, the pn junction capacitance of the MOS transistor is reset by applying the reset voltage to the first electrode of the MOS transistor and the capacitor is reset by the resetting means connected to the one terminal of the capacitor. Consequently, the capacitor can be reset more precisely at a higher speed.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having a cathode connected to a first DC (direct current) voltage; a first n-channel MOS transistor having a drain and a gate each connected to an anode of the photodiode and a source connected to a second DC voltage; a second n-channel MOS transistor having a gate connected to the gate of the first n-channel MOS transistor and a source connected to the second DC voltage through a capacitor; and a third n-channel MOS transistor having a drain connected to the source of the second n-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a source connected to an output signal line, wherein the first and second MOS transistors are biased to operate in a subthreshold region, a clock pulse is supplied to a drain of the second MOS transistor to set a voltage on the capacitor to an initial value such that the capacitor produces an output voltage proportional to the logarithm of the time integral of the quantity of incident light, and the third MOS transistor is so constituted to read the output voltage.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having a cathode connected to a first DC voltage; a first n-channel MOS transistor having a drain and a gate each connected to an anode of the photodiode and a source connected to a second DC voltage; a second n-channel MOS transistor having a drain connected to the first DC voltage, a gate connected to the gate of the first n-channel MOS transistor, and a source connected to the second DC voltage through a capacitor; a third n-channel MOS transistor having a drain connected to the source of the second n-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a source connected to an output signal line; and a fourth n-channel MOS transistor having a drain connected to the source of the second n-channel MOS transistor and to the capacitor, a gate connected to a reset line, and a source connected to the second DC voltage for determining an initial voltage on the capacitor, wherein the first and second MOS transistors are biased to operate in a subthreshold region, a voltage on the capacitor is set to the initial value by turning ON the fourth MOS transistor such that the capacitor produces an output voltage proportional to the logarithm of the time integral of the quantity of incident light, and the third MOS transistor is so constituted to read the output voltage.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having a cathode connected to a first DC voltage; a first n-channel MOS transistor having a drain and a gate each connected to an anode of the photodiode and a source connected to a second DC voltage; a second n-channel MOS transistor having a gate connected to the gate of the first n-channel MOS transistor; a fifth n-channel MOS transistor having a drain connected to a source of the second n-channel MOS transistor, a gate connected to an integration-time control line, and a source connected to the second DC voltage through a capacitor; and a third n-channel MOS transistor having a drain connected to the source of the fifth n-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a source connected to an output signal line, wherein the first and second MOS transistors are biased to operate in a subthreshold region, the fifth MOS transistor is turned ON upon application of a clock pulse to a drain of the second MOS transistor to set a voltage on the capacitor to an initial value such that the capacitor produces an output voltage proportional to the logarithm of the time integral of the quantity of incident light, an integration time is determined based on a period during which the fifth MOS transistor is in the OFF state to equalize the timing for integration in each of the pixels, and the third MOS transistor is so constituted to read the output voltage.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having a cathode connected to a first DC voltage; a first n-channel MOS transistor having a drain and a gate each connected to an anode of the photodiode and a source connected to a second DC voltage; a second n-channel MOS transistor having a gate connected to the gate of the first n-channel MOS transistor; a fifth n-channel MOS transistor having a drain connected to a source of the second n-channel MOS transistor, a gate connected to an integration-time control line, and a source connected to the second DC voltage through a capacitor; a third n-channel MOS transistor having a drain connected to the source of the fifth n-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a source connected to an output signal line; and a fourth n-channel MOS transistor having a drain connected to the source of the fifth n-channel MOS transistor and to the capacitor, a gate connected to a reset line, and al source connected to a third DC voltage for determining an initial voltage on the capacitor, wherein the first and second MOS transistors are biased to operate in a subthreshold region, a clock pulse is applied to a drain of the second MOS transistor to set a voltage on the source of the second MOS transistor and on the drain of the fifth MOS transistor to an initial value, a voltage on the capacitor is set to the initial value by turning ON the fourth MOS transistor such that the capacitor produces an output voltage proportional to the logarithm of the time integral of the quantity of incident light, an integration time is determined based on a period during which the drain of the second MOS transistor is at a HIGH-level voltage to equalize the timing for integration in each of the pixels, and the third MOS transistor is so constituted to read the output voltage even during a period of integration.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having an anode connected to a first DC voltage; a first p-channel MOS transistor having a drain and a gate each connected to a cathode of the photodiode and a source connected to a second DC voltage; a second p-channel MOS transistor having a gate connected to the gate of the first p-channel MOS transistor and a source connected to the second DC voltage through a capacitor; and a third p-channel MOS transistor having a source connected to the source of the second p-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a drain connected to an output signal line, wherein the first and second MOS transistors are biased to operate in a subthreshold region, a clock pulse is supplied to a drain of the second MOS transistor to set a voltage on the capacitor to an initial value such that the capacitor produces an output voltage proportional to the logarithm of the time integral of the quantity of incident light, and the third MOS transistor is so constituted to read the output voltage.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having an anode connected to a first DC voltage; a first p-channel MOS transistor having a drain and a gate each connected to a cathode of the photodiode and a source connected to a second DC voltage; a second p-channel MOS transistor having a drain connected to the first DC voltage, a gate connected to the gate of the first p-channel MOS transistor, and a source connected to the second DC voltage through a capacitor; a third p-channel MOS transistor having a source connected to the source of the second p-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a drain connected to an output signal line; and a fourth p-channel MOS transistor having a drain connected to the source of the second p-channel MOS transistor and to the capacitor, a gate connected to a reset line, and a source connected to the second DC voltage for determining an initial voltage on the capacitor, wherein the first and second MOS transistors are biased to operate in a subthreshold region, a voltage on the capacitor is set to the initial value by turning ON the fourth MOS transistor such that the capacitor produces an output voltage proportional to the logarithm of the time integral of the quantity of incident light, and the third MOS transistor is so constituted to read the output voltage.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having an anode connected to a first DC voltage; a first p-channel MOS transistor having a drain and a gate each connected to a cathode of the photodiode and a source connected to a second DC voltage; a second p-channel MOS transistor having a gate connected to the gate of the first p-channel MOS transistor; a fifth p-channel MOS transistor having a drain connected to a source of the second p-channel MOS transistor, a gate connected to an integration-time control line, and a source connected to the second DC voltage through a capacitor; and a third p-channel MOS transistor having a source connected to the source of the fifth p-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a drain connected to an output signal line, wherein the first and second MOS transistors are biased to operate in a subthreshold region, the fifth MOS transistor is turned ON upon application of a clock pulse to a drain of the second MOS transistor to set a voltage on the capacitor to an initial value such that the capacitor produces an output voltage proportional to the logarithm of the time integral of the quantity of incident light, an integration time is determined based on a period during which the fifth MOS transistor is in the OFF state to equalize the timing for integration in each of the pixels, and the third MOS transistor is so constituted to read the output voltage.
The objects of the present invention may also be achieved by a solid-state image pickup device comprising a semiconductor substrate, a plurality of pixels arranged in rows and columns on the substrate, and a scanning element for reading in time series respective signals from the pixels formed on the substrate, each of the pixels including: a pn-junction photodiode having an anode connected to a first DC voltage; a first p-channel MOS transistor having a drain and a gate each connected to a cathode of the photodiode and a source connected to a second DC voltage; a second p-channel MOS transistor having a gate connected to the gate of the first p-channel MOS transistor; a fifth p-channel MOS transistor having a drain connected to a source of the second p-channel MOS transistor, a gate connected to an integration-time control line, and a source connected to the second DC voltage through a capacitor; a third p-channel MOS transistor having a source connected to the source of the fifth p-channel MOS transistor and to the capacitor, a gate connected to a column select line, and a drain connected to an output signal line; and a fourth p-channel MOS transistor having a drain connected to the source of the fifth p-channel MOS transistor and to the capacitor, a gate connected to a reset line, and a source connected to a third DC voltage for determining an initial voltage on the capacitor, wherein the first and second MOS transistors are biased to operate in a subthreshold region, an integration time is determined based on a period during which a drain of the second MOS transistor is at a LOW-level voltage to equalize the timing for integration in each of the pixels, and the third MOS transistor is so constituted to read the output voltage even during a period of integration.